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XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
? Logic 0 = No TX break condition. (default)
? Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM/DLD) enable.
? Logic 0 = Data registers are selected. (default)
? Logic 1 = Divisor latch registers are selected.
3.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
? Logic 0 = Force DTR# output HIGH (default).
? Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
? Logic 0 = Force RTS# output HIGH (default).
? Logic 1 = Force RTS# output LOW. It is required to start Auto RTS Flow Control.
MCR[2]: GPIO[3:0] or Modem IO Select
This bit controls whether GPIO[3:0] behave as GPIO pins or as modem IO pins (RI#, CD#, DTR#, DSR#)
? Logic 0 = GPIO[3:0] behave as GPIO pins
? Logic 1 = GPIO[3:0] behave as RI#, CD#, DTR#, DSR#
In the Loopback Mode, this bit is used as the OP1# to write the state of the modem RI# interface signal.
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This bit is also used to control the OP2#
signal during internal loopback mode. This bit applies only to the Intel and VLIO bus modes. This bit has no
effect in the Motorola bus mode.
? Logic 0 = INT output disabled (three state). During internal loopback mode, OP2# is HIGH.
? Logic 1 = INT output enabled (active). During internal loopback mode, OP2# is LOW.
T ABLE 12: INT O UTPUT M ODES
MCR
B IT -3
0
1
INT O UTPUT
Three-State
Active
37
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